? semiconductor components industries, llc, 2013 may, 2013 ? rev. 7 1 publication order number: mc14526b/d mc14526b presettable 4-bit down counters the mc14526b binary counter is constructed with mos p ? channel and n ? channel enhancement mode devices in a monolithic structure. this device is presettable, cascadable, synchronous down counter with a decoded ?0? state output for divide ? by ? n applications. in single stage applications the ?0? output is applied to the preset enable input. the cascade feedback input allows cascade divide ? by ? n operation with no additional gates required. the inhibit input allows disabling of the pulse counting function. inhibit may also be used as a negative edge clock. this complementary mos counter can be used in frequency synthesizers, phase ? locked loops, and other frequency division applications requiring low power dissipation and/or high noise immunity. features ? supply voltage range = 3.0 vdc to 18 vdc ? logic edge ? clocked design: incremented on positive transition of clock or negative transition of inhibit ? asynchronous preset enable ? capable of driving two low ? power ttl loads or one low ? power schottky ttl load over the rated temperature range ? these devices are pb ? free and are rohs compliant ? nlv prefix for automotive and other applications requiring unique site and control change requirements; aec ? q100 qualified and ppap capable maximum ratings rating symbol value unit dc supply voltage range v dd ? 0.5 to +18.0 v input or output voltage range (dc or transient) v in , v out ? 0.5 to v dd + 0.5 v input or output current (dc or transient) per pin i in , i out 10 ma power dissipation per package (note 1) p d 500 mw operating temperature range t a ? 55 to +125 c storage temperature range t stg ? 65 to +150 c lead temperature (8 ? second soldering) t l 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. 1. temperature derating: plastic ?p and d/dw? packages: ? 7.0 mw/ c from 65 c to 125 c this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high ? impedance circuit. for proper operation, v in and v out should be constrained to the range v ss (v in or v out ) v dd . unused inputs must always be tied to an appropriate logic voltage level (e.g., either v ss or v dd ). unused outputs must be left open. http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. ordering information soic ? 16 wb dw suffix case 751g marking diagrams a = assembly location wl, l = wafer lot yy, y = year ww, w = work week g = pb ? free package 1 1 14526b awlywwg pdip ? 16 p suffix case 648 1 1 mc14526bcp awlyywwg
mc14526b http://onsemi.com 2 function table inputs output resulting function clock reset inhibit preset enable cascade feedback ?0? x x x h h h x x x l h x l l h l h h asynchronous reset* asynchronous reset asynchronous reset x l x h x l asynchronous preset l l l h l l x x l l decrement inhibited decrement inhibited h h l l l l l l l l l l l l l l l l l l no change** (inactive edge) no change** (inactive edge) decrement** decrement** x = don?t care notes: * * output ?0? is low when reset goes high only it pe and cf are low. ** output ?0? is high when reset is low, only if cf is high and count is 0000. pin descriptions preset enable (pin 3) ? if reset is low, a high level on the preset enable input asynchronously loads the counter with the programmed values on p0, p1, p2, and p3. inhibit (pin 4) ? a high level on the inhibit input pre ? vents the clock from decrementing the counter. with clock (pin 6) held high, inhibit may be used as a negative edge clock input. clock (pin 6) ? the counter decrements by one for each rising edge of clock. see the function table for level requirements on the other inputs. reset (pin 10) ? a high level on reset asynchronously forces q0, q1, q2, and q3 low and, if cascade feedback is high, causes the ?0? output to go high. ?0? (pin 12) ? the ?0? (zero) output issues a pulse one clock period wide when the counter reaches terminal count (q0 = q1 = q2 = q3 = low) if cascade feedback is high and preset enable is low. when presetting the counter to a value other than all zeroes, the ?0? output is valid after the rising edge of preset enable (when cascade feedback is high). see the function table. cascade feedback (pin 13) ? if the cascade feedback input is high, a high level is generated at the ?0? output when the count is all zeroes. if cascade feedback is low, the ?0? output depends on the preset enable input level. see the function table. p0, p1, p2, p3 (pins 5, 11, 14, 2) ? these are the preset data inputs. p0 is the lsb. q0, q1, q2, q3 (pins 7, 9, 15, 1) ? these are the synchronous counter outputs. q0 is the lsb. v ss (pin 8) ? the most negative power supply potential. this pin is usually ground. v dd (pin 16) ? the most positive power supply potential. v dd may range from 3.0 to 18 v with respect to v ss . state diagram mc14526b 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5
mc14526b http://onsemi.com 3 electrical characteristics (voltages referenced to v ss ) v dd vdc ? 55 c 25 c 125 c characteristic symbol min max min typ (note 2) max min max unit output voltage ?0? level v in = v dd or 0 ?1? level v in = 0 or v dd v ol 5.0 10 15 ? ? ? 0.05 0.05 0.05 ? ? ? 0 0 0 0.05 0.05 0.05 ? ? ? 0.05 0.05 0.05 vdc output voltage ?0? level v in = v dd or 0 ?1? level v in = 0 or v dd v oh 5.0 10 15 4.95 9.95 14.95 ? ? ? 4.95 9.95 14.95 5.0 10 15 ? ? ? 4.95 9.95 14.95 ? ? ? vdc input voltage ?0? level (v o = 4.5 or 0.5 vdc) (v o = 9.0 or 1.0 vdc) (v o = 13.5 or 1.5 vdc) ?1? level (v o = 0.5 or 4.5 vdc) (v o = 1.0 or 9.0 vdc) (v o = 1.5 or 13.5 vdc) v il 5.0 10 15 ? ? ? 1.5 3.0 4.0 ? ? ? 2.25 4.50 6.75 1.5 3.0 4.0 ? ? ? 1.5 3.0 4.0 vdc input voltage ?0? level (v o = 4.5 or 0.5 vdc) (v o = 9.0 or 1.0 vdc) (v o = 13.5 or 1.5 vdc) ?1? level (v o = 0.5 or 4.5 vdc) (v o = 1.0 or 9.0 vdc) (v o = 1.5 or 13.5 vdc) v ih 5.0 10 15 3.5 7.0 11 ? ? ? 3.5 7.0 11 2.75 5.50 8.25 ? ? ? 3.5 7.0 11 ? ? ? vdc output drive current (v oh = 2.5 vdc) source (v oh = 4.6 vdc) (v oh = 9.5 vdc) (v oh = 13.5 vdc) (v ol = 0.4 vdc) sink (v ol = 0.5 vdc) (v ol = 1.5 vdc) i oh 5.0 5.0 10 15 ? 3.0 ? 0.64 ? 1.6 ?4.2 ? ? ? ? ?2.4 ?0.51 ?1.3 ?3.4 ?4.2 ?0.88 ?2.25 ?8.8 ? ? ? ? ?1.7 ?0.36 ?0.9 ?2.4 ? ? ? ? madc i ol 5.0 10 15 0.64 1.6 4.2 ? ? ? 0.51 1.3 3.4 0.88 2.25 8.8 ? ? ? 0.36 0.9 2.4 ? ? ? madc input current i in 15 ? 0.1 ? 0.00001 0.1 ? 1.0 adc input capacitance (v in = 0) c in ? ? ? ? 5.0 7.5 ? ? pf quiescent current (per package) 5.0 10 15 ? ? ? 5.0 10 20 ? ? ? 0.005 0.010 0.015 5.0 10 20 ? ? ? 150 300 600 adc total supply current (notes 3, 4) (dynamic plus quiescent, per package) (c l = 50 pf on all outputs, all buffers switching) 5.0 10 15 i t = (1.7 a/khz) f + i dd i t = (3.4 a/khz) f + i dd i t = (5.1 a/khz) f + i dd adc 2. data labelled ?typ? is not to be used for design purposes but is intended as an indication of the ic?s potential performance. 3. the formulas given are for the typical characteristics only at 25 c. 4. to calculate total supply current at loads other than 50 pf: i t (c l ) = i t (50 pf) + (c l ? 50) vfk where: i t is in a (per package), c l in pf, v = (v dd ? v ss ) in volts, f in khz is input frequency, and k = 0.001.
mc14526b http://onsemi.com 4 ????????????????????????????????? ????????????????????????????????? (c l = 50 pf, t a = 25 c) (note 5) characteristic symbol v dd min typ (note 6) max unit output rise and fall time t tlh , t thl = (1.5 ns/pf) c l + 25 ns t tlh , t thl = (0.75 ns/pf) c l + 12.5 ns t tlh , t thl = (0.55 ns/pf) c l + 9.5 ns t tlh , t thl (figures 4, 5) 5.0 10 15 ? ? ? 100 50 40 200 100 80 ns propagation delay time (inhibit used as negative edge clock) clock or inhibit to q t plh , t phl = (1.7 ns/pf) c l + 465 ns t plh , t phl = (0.66 ns/pf) c l + 197 ns t plh , t phl = (0.5 ns/pf) c l + 135 ns clock or inhibit to ?0? t plh , t phl = (1.7 ns/pf) c l + 155 ns t plh , t phl = (0.66 ns/pf) c l + 87 ns t plh , t phl = (0.5 ns/pf) c l + 65 ns t plh , t phl (figures 4, 5, 6) 5.0 10 15 ? ? ? 550 225 160 1100 450 320 ns 5.0 10 15 ? ? ? 240 130 100 480 260 200 propagation delay time pn to q t plh , t phl (figures 4, 7) 5.0 10 15 ? ? ? 260 120 100 520 240 200 ns propagation delay time reset to q t phl (figure 8) 5.0 10 15 ? ? ? 250 110 80 500 220 160 ns propagation delay time preset enable to ?0? t phl , t plh (figures 4, 9) 5.0 10 15 ? ? ? 220 100 80 440 200 160 ns clock or inhibit pulse width t w (figures 5, 6) 5.0 10 15 250 100 80 125 50 40 ? ? ? ns clock pulse frequency (with pe = low) f max (figures 4, 5, 6) 5.0 10 15 ? ? ? 2.0 5.0 6.6 1.5 3.0 4.0 mhz clock or inhibit rise and fall time t r , t f (figures 5, 6) 5.0 10 15 ? ? ? ? ? ? 15 5 4 s setup time pn to preset enable t su (figure 1) 5.0 10 15 90 50 40 40 15 10 ? ? ? ns hold time preset enable to pn t h (figure 2) 5.0 10 15 30 30 30 ? 15 ? 5 0 ? ? ? ns preset enable pulse width t w (figure 3) 5.0 10 15 250 100 80 125 50 40 ? ? ? ns reset pulse width t w (figure 8) 5.0 10 15 350 250 200 175 125 100 ? ? ? ns reset removal time t rem (figure 8) 5.0 10 15 10 20 30 ? 110 ? 30 ? 20 ? ? ? ns 5. the formulas given are for the typical characteristics only at 25 c. 6. data labelled ?typ? is not to be used for design purposes but is intended as an indication of the ic?s potential performance.
mc14526b http://onsemi.com 5 figure 1. typical output source characteristics test circuit figure 2. typical output sink characteristics test circuit cf pe p0 p1 p2 p3 reset inhibit clock q0 q1 q2 q3 0 v ss v dd = -v gs v oh i oh external power supply cf pe p0 p1 p2 p3 reset inhibit clock q0 q1 q2 q3 0 v ss v dd = v gs v ol i ol external power supply figure 3. power dissipation figure 4. test circuit cf pe p0 p1 p2 p3 reset inhibit clock q0 q1 q2 q3 0 v ss v dd c l c l c l c l c l pulse generator 20 ns 20 ns clock 90% 10% 50% variable width 50% duty cycle v ss v dd device under test test point q or 0 c l * *includes all probe and jig capacitance.
mc14526b http://onsemi.com 6 switching waveforms figure 5. figure 6. v dd v ss v dd v ss v dd v ss v dd v ss v dd v ss v dd v ss v dd v ss t r t f t r t f t f t r t r t f v dd clock any p any q any q clock reset t plh t phl t plh t phl t phl t plh preset enable preset enable any p gnd t w t w t w t w any q or 0 any q or 0 t tlh t thl 1/f max 1/f max 90% 50% 10% 90% 50% 10% 90% 50% 10% 90% 50% 10% 90% 50% 10% 50% 0 50% 90% 50% 10% t tlh t thl inhibit t plh t phl t phl 50% 50% 50% t su t h 50% 50% valid figure 7. figure 8. figure 9. figure 10. t rem
mc14526b http://onsemi.com 7 mc14526b logic diagram (binary down counter) cf pe inhibit clock reset 13 3 4 6 10 p0 q0 p1 q1 p2 q2 p3 q3 5711 9 14 15 2 1 12 0 d c t r q pe q d c t r q pe q d c t r q pe q d c t r pe q v dd v dd applications information divide ? by ? n, single stage figure 11 shows a single stage divide ? by ? n application. to initialize counting a number, n is set on the parallel inputs (p0, p1, p2, and p3) and reset is taken high asynchronously. a zero is forced into the master and slave of each bit and, at the same time, the ?0? output goes high. because preset enable is tied to the ?0? output, preset is enabled. reset must be released while the clock is high so the slaves of each bit may receive n before the clock goes low. when the clock goes low and reset is low, the ?0? output goes low (if p0 through p3 are unequal to zero). the counter downcounts with each rising edge of the clock. when the counter reaches the zero state, an output pulse occurs on ?0? which presets n. the propagation delays from the clock?s rising and falling edges to the ?0? output?s rising and falling edges are about equal, making the ?0? output pulse approximately equal to that of the clock pulse. the inhibit pin may be used to stop pulse counting. when this pin is taken high, decrementing is inhibited. cascaded, presettable divide ? by ? n figure 12 shows a three stage cascade application. t aking reset high loads n. only the first stage?s reset pin (least significant counter) must be taken high to cause the preset for all stages, but all pins could be tied together, as shown. when the first stage?s reset pin goes high, the ?0? output is latched in a high state. reset must be released while clock is high and time allowed for preset enable to load n into all stages before clock goes low. when preset enable is high and clock is low, time must be allowed for the zero digits to propagate a cascade feedback to the first non ? zero stage. worst case is from the most significant bit (m.s.b.) to the l.s.b., when the l.s.b. is equal to one (i.e. n = 1). after n is loaded, each stage counts down to zero with each rising edge of clock. when any stage reaches zero and the leading stages (more significant bits) are zero, the ?0? output goes high and feeds back to the preceding stage. when all stages are zero, the preset enable automatically loads n while the clock is high and the cycle is renewed.
mc14526b http://onsemi.com 8 figure 11. n counter p0 p1 p2 p3 cf reset inhibit clock pe q0 q1 q2 q3 0 n v dd v ss f in buffer f in n figure 12. 3 stages cascaded n0 n1 n2 n3 n4 n5 n6 n7 p0 p1 p2 p3 q0 q1 q2 q3 f in clock inhibit v ss v dd load n v ss reset 0 pe cf 10 k v ss p0 p1 p2 p3 q0 q1 q2 q3 clock inhibit reset 0 pe cf clock inhibit reset 0 pe cf p0 p1 p2 p3 q0 q1 q2 q3 n8 n9 n10 n11 v ss v dd buffer lsb msb f in n ordering information device package shipping ? MC14526BCPG pdip ? 16 (pb ? free) 500 units / rail mc14526bdwg soic ? 16 (pb ? free) 47 units / rail mc14526bdwr2g soic ? 16 (pb ? free) 1000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
mc14526b http://onsemi.com 9 package dimensions soic ? 16 wb case 751g ? 03 issue d d 14x b 16x seating plane s a m 0.25 b s t 16 9 8 1 h x 45 m b m 0.25 h 8x e b a e t a1 a l c notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimensions d and e do not inlcude mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.13 total in excess of the b dimension at maximum material condition. dim min max millimeters a 2.35 2.65 a1 0.10 0.25 b 0.35 0.49 c 0.23 0.32 d 10.15 10.45 e 7.40 7.60 e 1.27 bsc h 10.05 10.55 h 0.25 0.75 l 0.50 0.90 q 0 7 11.00 16x 0.58 16x 1.62 1.27 dimensions: millimeters 1 pitch soldering footprint
mc14526b http://onsemi.com 10 package dimensions notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. ? a ? b f c s h g d j l m 16 pl seating 18 9 16 k plane ? t ? m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01 pdip ? 16 case 648 ? 08 issue t on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 mc14526b/d eclinps is a trademark of semiconductor components industries, llc (scillc). literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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